1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory and a method for driving the same. More particularly, it relates to a semiconductor memory composed of an MFS transistor including a field effect transistor having a gate electrode formed on a ferroelectric film, an MFIS transistor including a field effect transistor having a gate electrode formed on a multi-layer film of a ferroelectric film and a dielectric film or an MFMIS transistor including a ferroelectric capacitor formed on a gate electrode of a field effect transistor, and a method for driving the same.
2. Description of the Related Art
Known one-transistor type nonvolatile semiconductor memories having a ferroelectric film are three types of transistors, that is, an MFS transistor, an MFIS transistor and an MFMIS transistor.
An MFS transistor has a Metal/Ferroelectric/Semiconductor multi-layer structure and includes a gate insulating film of a ferroelectric film directly formed on a channel region of a semiconductor substrate.
An MFIS transistor has a Metal/Ferroelectric/Insulator/Semiconductor multi-layer structure and includes a dielectric film serving as a buffer layer formed between a gate insulating film of a ferroelectric film and a semiconductor substrate. The MFIS transistor is improved in the surface characteristic as compared with the MFS transistor.
An MFMIS transistor has a Metal/Ferroelectric/Metal/Insulator/Semiconductor multi-layer structure and includes a ferroelectric capacitor formed on a gate electrode of a field effect transistor having the MOS structure. The MFMIS transistor is formed in either of the following two known structures: In the first structure, the ferroelectric capacitor is formed above the gate electrode of the field effect transistor with an insulating film sandwiched therebetween; and in the second structure, the gate electrode of the field effect transistor also works as the lower electrode of the ferroelectric capacitor.
In a memory cell using, as a data storing transistor, a one-transistor type nonvolatile semiconductor memory having a ferroelectric film (namely, a nonvolatile memory), the memory cell is constructed by connecting a transistor for gate selection and a transistor for source selection to a data storing transistor of an MFS transistor as disclosed in, for example, Japanese Patent No. 2921812.
FIG. 6 shows the circuit configuration of the one-transistor type nonvolatile semiconductor memory described in Japanese Patent No. 2921812. In FIG. 6, WL denotes a word line for write, RL denotes a word line for read, GL denotes an operation voltage supply line, BL denotes a bit line, Q1 denotes a data storing transistor, Q2 denotes a writing transistor and Q3 denotes a reading transistor.
The gate of the data storing transistor Q1 is connected to the operation voltage supply line GL through the writing transistor Q2, the drain of the data storing transistor Q1 is connected to the bit line BL through the reading transistor Q3, and the source of the data storing transistor Q1 is grounded. A memory cell array is formed by arranging a plurality of memory cells each having this circuit configuration on a silicon substrate.
A data erase operation, a data write operation and a data read operation of the memory cell having this circuit configuration will now be described with reference to FIG. 7.
In the data erase operation, negative potential is applied to a well region of a semiconductor substrate so as to apply a voltage between the gate of each data storing transistor Q1 and the substrate. Thus, the polarization of ferroelectric films are turned along the same direction. In this manner, data stored in all the memory cells are erased.
In the data write operation, a voltage is applied between the substrate and the gate of the data storing transistor Q1 of the memory cell disposed in an address selected by the writing transistor Q2, so as to reverse the polarization direction of the ferroelectric film of this transistor (to place it in an on-state) or the polarization direction of the ferroelectric film of the transistor is kept (to place it in an off-state) without applying the voltage between the gate and the substrate. Specifically, a data is written by causing either of two kinds of polarized states, that is, to reverse the polarization (which corresponds to an on-state) and to keep the polarization (which corresponds to an off-state) in accordance with the input data. Since the polarized state of the ferroelectric film is kept without applying a voltage, the memory cell functions as a nonvolatile semiconductor memory.
In the data read operation, the reading transistor Q3 is turned on, so as to detect voltage drop accompanied by a current flowing from the bit line BL through the channel of the data storing transistor Q1 to a ground line (namely, a drain-source current). Since the channel resistance is varied depending upon the polarized state of the ferroelectric film of the data storing transistor Q1, a data written in the data storing transistor Q1 can be thus read.
In driving the nonvolatile semiconductor memory, the efficiency of the read operation is improved by setting the threshold voltage of the data storing transistor Q1 to a gate voltage VG for maximizing a difference between the drain-source current Ids on a subthreshold curve of the data storing transistor Q1 obtained when the polarization direction of the ferroelectric film is reversed (namely, in an on-state) and the drain-source current Ids on a subthreshold curve of the data storing transistor Q1 obtained when the polarization direction of the ferroelectric film is not reversed (namely, in an off-state).
The conventional nonvolatile semiconductor memory, however, has an unavoidable problem that a read voltage is lowered (namely, a drain-source voltage is lowered) with time.
In consideration of the conventional problem, an object of the invention is improving the retention characteristic of a nonvolatile semiconductor memory, namely, improving (a drain-source current Idsxe2x80x2 after time)/(a drain-source current Ids in initial state), by suppressing the phenomenon that the read voltage is lowered with time.
In order to achieve the object, the present inventors have carried out experiments with paying attention to a read voltage (a drain-source voltage) employed in a read operation, which is conventionally minimally considered. As a result, it has been found that degradation of a drain-source current IDS can be suppressed by setting the read voltage to a value belonging to a drain non-saturated region (i.e., a region where the drain-source current depends upon the drain-source voltage) of a field effect transistor included in a semiconductor memory. The method for driving a semiconductor memory of this invention was devised on the basis of this finding.
Specifically, the first method of this invention for driving a semiconductor memory composed of an MFS transistor including a field effect transistor having a gate electrode formed on a ferroelectric film or an MFIS transistor including a field effect transistor having a gate electrode formed on a multi-layer film of a ferroelectric film and a dielectric film, comprises the steps of writing a data in the semiconductor memory by changing a polarized state of the ferroelectric film by applying a voltage to the gate electrode; and reading a data written in the semiconductor memory by detecting a current change appearing between a drain and a source of the field effect transistor by applying a voltage between the drain and the source of the field effect transistor with a voltage applied to the gate electrode, and magnitude of the voltage applied between the drain and the source of the field effect transistor in the step of reading a data is set within a range where a drain-source current of the field effect transistor increases as a drain-source voltage thereof increases.
The second method of this invention for driving a semiconductor memory composed of an MFMIS transistor including a ferroelectric capacitor formed above a gate electrode of a field effect transistor and having a control gate composed of an upper electrode of the ferroelectric capacitor, comprises the steps of writing a data in the semiconductor memory by changing a polarized state of a ferroelectric film of the ferroelectric capacitor by applying a voltage to the control gate; and reading a data written in the semiconductor memory by detecting a current change appearing between a drain and a source of the field effect transistor by applying a voltage between the drain and the source of the field effect transistor with a voltage applied to the control gate, and magnitude of the voltage applied between the drain and the source of the field effect transistor in the step of reading a data is set within a range where a drain-source current of the field effect transistor increases as a drain-source voltage thereof increases.
In the first or second method for driving a semiconductor memory of this invention, the magnitude of the voltage applied between the drain and the source of the field effect transistor in the step of reading a data, namely, the magnitude of the read voltage, is set within the range where the drain-source current of the field effect transistor increases as the drain-source voltage of the field effect transistor increases. Accordingly, the lowering of the drain-source current with time can be suppressed.
The first semiconductor memory of this invention composed of an MFS transistor including a field effect transistor having a gate electrode formed on a ferroelectric film or an MFIS transistor including a field effect transistor having a gate electrode formed on a multi-layer film of a ferroelectric film and a dielectric film, comprises first voltage supply means for supplying a first voltage to the gate electrode for changing a polarized state of the ferroelectric film in data write; and second voltage supply means for supplying a second voltage between a drain and a source of the field effect transistor in data read, and magnitude of the second voltage supplied by the second voltage supply means is set within a range where a drain-source current of the field effect transistor increases as a drain-source voltage thereof increases.
The second semiconductor memory of this invention composed of an MFMIS transistor including a ferroelectric capacitor formed above a gate electrode of a field effect transistor, comprises a control gate composed of an upper electrode of the ferroelectric capacitor; first voltage supply means for supplying a first voltage to the control gate for changing a polarized state of the ferroelectric film in data write; and second voltage supply means for supplying a second voltage between a drain and a source of the field effect transistor in data read, and magnitude of the second voltage supplied by the second voltage supply means is set within a range where a drain-source current of the field effect transistor increases as a drain-source voltage thereof increases.
In the first or second semiconductor memory of this invention, the magnitude of the second voltage applied between the drain and the source of the field effect transistor by the second voltage supply means in the data read is set within the range where the drain-source current of the field effect transistor increases as the drain-source voltage of the field effect transistor increases. Accordingly, the lowering of the drain-source current with time can be suppressed.